Description
Traditional serial communications are normally implemented using a device known as a UART, which translates data from the computer bus's internal parallel format to serial and back. This allows the computer to send data serially simply by doing a regular parallel write to an I/O register, and the UART will convert this to serial form and send it. Generally there were different UARTs for each computer architecture, with the goal of being as low-cost as possible. A good example is the Zilog Z-80 SIO from 1977, designed to work with the widely used Zilog Z80 to provide two serial ports with relatively high speeds up to 800 kbit/s. The SIO is technically a USART, as it understands synchronous protocols.1
The SCC is essentially an updated version of the SIO, with more internal logic to allow it to directly implement a number of common data link layer protocols. To start with, the SCC included a hardware implementation of the cyclic redundancy check (CRC), which allowed it to check, flag and reject improper data without the support of the host computer. Higher-level protocols included BiSync, HDLC and SDLC. HDLC is better known in its implementation in the modem-oriented LAPM protocol, part of V.42. By moving the implementation of these protocols to hardware, the SCC made it easy to implement local area networking systems, like IBM's SNA, without the need for the host CPU to handle these details.
When used in traditional serial mode, the SCC could be set to use 5, 6, 7 or 8 bits/character, 1, 1+1⁄2, or 2 stop bits, odd, even or no parity, and automatically detected or generated break signals. In synchronous modes, data could be optionally sent with NRZ, NRZI or FM encoding, as well as Manchester decoding, although Manchester encoding had to be handled in external logic.
The SCC's transmission rate could be timed from three sources. For basic RS-232-style communications, the SCC included an internal 300 Hz clock that could be multiplied by 1, 16, 32 to 64, providing data rates between 300 and 19,200 bit/s. Alternately, it could use the clock on the bus as provided by the host platform, and then divide that clock by 4, 8, 16 or 32 (the later two only in the original NMOS implementation). When used on a machine running at the common 8 MHz clock, this allowed for rates as high as 2 Mbit/s. Finally, the SCC also included inputs for the provision of an external clock. This worked similar to the host clock, but could be used to provide any reference clock signal, independent of the host platform. In this mode, the clock could be divided as in the internal case, or multiplied by 2 for even higher speeds, up to 32.3 Mbit/s in some versions. Using the external clock made it easy to implement LAN adaptors, which normally ran at speeds that were independent of the host computer.
Early implementations used receive buffers that were only 3 bytes deep, and a send buffer with a single byte. This meant that the real-world performance was limited by the host platform's ability to continually empty the buffers into its own memory. With network-like communications the SCC itself could cause the remote sender to stop transmission when the buffers were full, and thereby prevent data loss while the host was busy. With conventional async serial this was not possible; on the Macintosh Plus this limited RS-232 performance to about 9600 bit/s or less, and as little as 4800 bit/s on earlier models.
Most SCC models were available in either dual in-line package (DIP) or chip carrier (PLCC) versions.
Versions
- Z8030
Original model implemented in NMOS with a multiplexed "Z-Bus" interface that matched the Zilog Z8000/Z16C00/8086 CPUs.
- Z8530
Functionally identical to the Z8030, but using a non-multiplexed "Universal-Bus" designed to allow use with any CPU or host platform, including the Z80.
- Z8031 and Z8531
Versions of the Z8030 and Z8530 with the synchronous support removed, producing a design more closely matching the original SIO.2
- Z80C30 and Z85C30
CMOS implementations of the Z8030 and Z8530. Plug compatible with the early versions, adding the 2x speed when used with the external clock, and a number of bug fixes and improvements in the link layer protocols.
- Z80230 and Z85230
Updated CMOS implementations of the Z80C30 and Z85C30, also known as the ESCC.
- Z85233
Updated version of the Z85230 (only), also known as the EMSCC.
